1. Field
The present disclosure pertains to the field of information processing, and more particularly, to the field of error detection and correction in information processing systems.
2. Description of Related Art
As improvements in integrated circuit manufacturing technologies continue to provide for denser circuitry, lower operating voltages are being used to reduce power consumption. However, in memory structures such as static random access memory used as cache memory in processors, the combination of larger array sizes and lower operating voltage increases the likelihood of memory cell failure. Therefore, makers and users of these devices are becoming increasingly concerned with error detection and correction. Memory structures may be protected with the addition of parity and/or error-correcting-code (ECC) cells along with hardware to generate and check the parity and ECC values. Parity may provide for error detection which may be insufficient to provide a robust solution to error management. On the other hand, the cost of ECC in terms of die area and pipeline complexity may be too great to provide a desired solution.